Semiconductor memory device and operating method thereof

ABSTRACT

Provided herein are a semiconductor memory device and an operating method thereof. The semiconductor memory device may include a memory cell array, peripheral circuits, and a control logic. The memory cell array may include a plurality of memory strings. The peripheral circuits may program the memory cell array. The control logic may control the peripheral circuits and execute instructions for performing a first program operation by applying a program voltage to at least two selected word lines, among a plurality of word lines of the memory cell array, at a same time, and, after the first program operation, performing a second program operation by applying the program voltage to each of the selected word lines one at a time.

CROSS-REFERENCE TO RELATED APPLICATION

The present application is a continuation application of U.S.application Ser. No. 15/174,398, filed on Jun. 6, 2016, and claimspriority to Korean patent application number 10-2016-0002190 filed onJan. 7, 2016, the entire disclosure of which is incorporated herein byreference.

BACKGROUND

1. Technical Field

Various embodiments of the present disclosure relate to an electronicdevice, and more particularly to a semiconductor memory device and anoperating method thereof.

2. Related Art

A semiconductor memory device is one of the examples of semiconductordevices. The semiconductor memory devices may be classified intovolatile memory devices and nonvolatile memory devices.

The nonvolatile memory device can retain its data even in the absence ofa power source, although it may have a slow read and write speed. Thenonvolatile memory device may be used for the task of secondary storage,which does not lose the data when the device is powered down. Examplesof the nonvolatile memory device may include a read-only memory (ROM), amask ROM (MROM), a programmable ROM (PROM), an erasable programmable ROM(EPROM), an electrically erasable programmable ROM (EEPROM), a flashmemory, phase-change random access memory (PRAM), a magnetic RAM (MRAM),a resistive RAM (RRAM), a ferroelectric RAM (FRAM), etc. The flashmemory may be classified into a NOR type and a NAND type.

Like a random access memory (RAM), the flash memory can be written anderased multiple times, and like the ROM, the flash memory can retain itsdata even when power is interrupted. Recently, the flash memory iswidely used as a storage medium of portable electronic devices such as adigital camera, a smartphone, a personal digital assistant (PDA) andMP3.

SUMMARY

In an embodiment of the present disclosure, a semiconductor memorydevice may include a memory cell array, peripheral circuits, and acontrol logic. The memory cell array may include a plurality of memorystrings. The peripheral circuits may program the memory cell array. Thecontrol logic may control the peripheral circuits and executeinstructions for performing a first program operation by applying aprogram voltage to at least two selected word lines, among a pluralityof word lines of the memory cell array, at a same time, and, after thefirst program operation, performing a second program operation byapplying the program voltage to each of the selected word lines one at atime.

In an embodiment of the present disclosure, a semiconductor memorydevice may include a memory cell array, peripheral circuits, and acontrol logic. The memory cell array may include a plurality of memorystrings. The peripheral circuits may program the memory cell array. Thecontrol logic may control the peripheral circuits so as to perform afirst program operation by applying a program voltage to at least twoselected word lines, among a plurality of word lines of the memory cellarray, at a same time, and, after the first program operation, perform asecond program operation by applying the program voltage to each of theselected word lines one at a time. The peripheral circuits may becontrolled such that a start program voltage of the second programoperation is set using a last program voltage of the first programoperation.

In an embodiment of the present disclosure, a method of operating asemiconductor memory device may include storing a plurality of data bitsin page buffers coupled to a memory cell array through bit lines, thememory cell array including a plurality of memory strings, adjusting apotential level of the bit lines depending on the plurality of databits, performing a first program operation by simultaneously applying aprogram voltage to at least two selected word lines of a plurality ofword lines of the memory cell array, and performing, after the firstprogram operation, a second program operation by applying the programvoltage to each of the selected word lines one at a time.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating an example configuration of asemiconductor memory device according to an embodiment of the presentdisclosure.

FIG. 2 is a diagram illustrating an example configuration of a memoryblock of FIG. 1.

FIG. 3 is a flowchart illustrating an example of a program operation ofthe semiconductor memory device according to an embodiment of thepresent disclosure.

FIG. 4 is a diagram illustrating voltage levels of program pulsesapplied to selected word lines according to an embodiment of the presentdisclosure.

FIG. 5 is a flowchart illustrating an example of a program operation ofa semiconductor memory device according to an embodiment of the presentdisclosure.

FIG. 6 is a diagram illustrating voltage levels of program pulsesapplied to selected word lines according to an embodiment of the presentdisclosure.

FIG. 7 is a diagram illustrating an example of a memory system includingthe semiconductor memory device of FIG. 1.

FIG. 8 is a diagram illustrating an application example of the memorysystem of FIG. 7.

FIG. 9 is a diagram illustrating an example of a computing systemincluding the memory system illustrated with reference to FIG. 8.

DETAILED DESCRIPTION

Advantages and features of the present disclosure, and methods forachieving the same will be cleared with reference to exemplaryembodiments described later in detail together with the accompanyingdrawings. Accordingly, the present disclosure is not limited to thefollowing embodiments but may be embodied in other types. Rather, theseembodiments are provided so that the present disclosure will be thoroughand complete, and will fully convey the technical spirit of thedisclosure to those skilled in the art.

It will be understood that when an element is referred to as being“coupled” to another element, it may be directly coupled to the otherelement or intervening elements may be present therebteween. In thespecification, when an element is referred to as “comprising” or“including” a component, it does not preclude another component but mayfurther include other components unless the context clearly indicatesotherwise.

FIG. 1 is a diagram illustrating an example configuration of asemiconductor memory device according to an embodiment of the presentdisclosure.

Referring to FIG. 1, a semiconductor memory device 100 may include amemory cell array 110, peripheral circuits 120, 130 and 150, and acontrol logic 140. The peripheral circuits 120, 130 and 150 may includean address decoder 120, a page buffer circuit 130 and a voltagegeneration circuit 150.

The memory cell array 110 may have a plurality of memory cells that areorganized into a plurality of memory blocks 110MB. The plurality ofmemory cells belonging to a memory block 110MB may be organized into apage. The memory cell array 110 may be coupled to the address decoder120 through a plurality of word lines WL. The memory cell array 110 maybe coupled to the page buffer circuit 130 through bit lines BL1 to BLm.In an embodiment, the plurality of memory cells may be nonvolatilememory cells. In an embodiment, the memory cells coupled to the sameword line may be defined as one page.

In an embodiment, the memory cells of the memory cell array 110 may bearranged in a plurality of memory strings. Each memory string mayinclude a drain select transistor, a plurality of memory cells, and asource select transistor, which are coupled in series between a bit lineand a source line.

The address decoder 120, the page buffer circuit 130, and the voltagegeneration circuit 150 may be used as peripheral circuits for drivingthe memory cell array 110.

The address decoder 120 may be coupled to the memory cell array 110through the word lines WL. The address decoder 120 may operate under thecontrol of the control logic 140. The address decoder 120 may receiveaddresses ADDR through an input/output buffer (not illustrated) providedin the semiconductor memory device 100.

The address decoder 120 may decode a row address of the receivedaddresses ADDR. The address decoder 120 may apply, during a programoperation, a program voltage Vpgm, a pass voltage Vpass, a verifyvoltage Vverify, and a plurality of operation voltages, which aregenerated from the voltage generation circuit 150, to the memory cellsand the drain and source select transistors of the memory cell array 110in accordance with the decoded row address.

The address decoder 120 may decode the addresses ADDR to extract columnaddresses. The address decoder 120 may transmit the decoded columnaddress Yi to the page buffer circuit 130.

Addresses ADDR received in response to a request for a program operationmay include a block address, a row address, and a column address Yitherein. The address decoder 120 may select one memory block accordingto the block address and the column address, and then may select morethan one word line WL at once or select only one word line WL. Thecolumn address Yi is decoded by the address decoder 120 and provided tothe page buffer circuit 130.

The page buffer circuit 130 may include a plurality of page buffers PB1to PBm. The plurality of page buffers PB1 to PBm may be coupled to thememory cell array 110 through the bit lines BL1 to BLm. Each of the pagebuffers PB1 to PBm may temporarily store data DATA to be programmedduring the program operation and control a bit line voltage of acorresponding one of the bit lines BL1 to BLm in accordance with thetemporarily stored program data DATA. The page buffer circuit 130 mayoperate under the control of the control logic 140.

The control logic 140 may be coupled to the address decoder 120, thepage buffer circuit 130, and the voltage generation circuit 150. Inresponse to a command signal CMD and a control signal CTRL, the controllogic 140 may provide a voltage control signal VCON for the voltagegeneration circuit 150 to generate operation voltages Vpgm, Vverify andVpass.

In an embodiment, the control logic 140 may apply program voltages Vpgmin different manners depending on whether it is in a first programoperation or a second program operation. During the first programoperation, the control logic 140 may apply a program voltage Vpgm at thesame time to at least two selected word lines coupled to the memory cellarray 110 and control the peripheral circuits 120, 130 and 150 toperform the first program operation. The control logic 140 may performthe second program operation after performing the first programoperation. In the second program operation, the control logic 140 mayselect one word line at a time. The control logic 140 may apply theprogram voltage Vpgm to one word line at a time, and may control theperipheral circuits 120, 130 and 150 to perform the second programoperation. Each of the first and second program operations may beperformed by an incremental step pulse program (ISPP) method in whichthe program voltage is controlled such that it gradually increases by astep voltage each time.

The voltage generation circuit 150 may generate, in response to avoltage control signal VCON outputted from the control logic 140, theoperation voltages Vpgm, Vverify and Vpass that are used for the overalloperations of the memory cells.

FIG. 2 is a diagram illustrating an example configuration of a memoryblock of FIG. 1.

Referring to FIG. 2, one of the memory blocks of FIG. 1 will bediscussed as an example.

Although the present embodiment performs the program operation in amanner that stores two bits of data in a unit cell, which may be calleda multi level cell (MLC), the present disclosure is not limited thereto.For example, various embodiments of the present disclosure may beapplied to other kinds of memory cells, such as a triple level cell(TLC), a quad level cell (QLC), etc., having various threshold voltagelevels.

Referring to FIG. 2, the memory block 110MB may include a plurality ofmemory strings ST1 to STm, which are coupled between the bit lines BL1to BLm and a common source line CSL. For instance, the bit lines BL1 toBLm may be respectively coupled to the plurality of memory strings ST1to STm. The common source line CSL may be coupled in common to theplurality of memory strings ST1 to STm.

Hereinafter, a first memory string ST1, which is one of the memorystrings ST1 to STm, will be described as an example.

The first memory string ST1 may include a source select transistor SST,a plurality of memory cells C0 to Cn, and a drain select transistor DST,which are coupled in series to each other between the common source lineCSL and the first bit line BL1. Gates of the source select transistorsSST coupled to the different memory strings ST1 to STm may be coupled tothe source select line SSL. Gates of the memory cells C0 to Cn may berespectively coupled to the word lines WL0 to WLn. Gates of the drainselect transistors DST may be coupled to the drain select line DSL.

The memory cells included in the memory block 110MB may be classified ina physical page unit or a logical page unit.

When the program operation is performed on the basis of the MLC, memorycell states that a single memory cell can have may be classified into anerase state, a PV1 state, a PV2 state, and a PV3 state. Here, the PV1,PV2, and PV3 states may be programmed threshold voltage distributions.For example, the PV1 state may be the lowest programmed thresholdvoltage distribution, and the PV3 state may be the highest programmedthreshold voltage distribution. The PV2 state may be a programmedthreshold voltage distribution between the PV1 and PV3.

Although the present embodiment selects a first word line WL0 and asecond word line WL1 respectively corresponding to first and secondpages PAGE_0 and PAGE_1 of the selected memory block 110MB of the memorycell array 110, the present disclosure is not limited thereto.Alternatively, two or more word lines among the plurality of word linesWL0 to WLn may be selected and used.

In an embodiment of the present disclosure, the first program operationis performed first, and then the second program operation is performed.In the first program operation, a program voltage Vpgm may be applied atthe same time to at least two selected word lines among the word linesWL0 to WLn coupled to the plurality of memory cells. In the secondprogram operation, a program voltage Vpgm may be applied to the selectedword lines one at a time in a predetermined order. The first and secondprogram operations may be performed using ISPP method, and thud theprogram voltage Vpgm may be increased stepwise.

For example, in the first program operation, a program operation may beperformed by applying a program voltage Vpgm at the same time to thefirst memory cell C0 and the second memory cell C1, among the pluralityof memory cells C0 to Cn included in the first memory string ST1. Inthis case, each of the first and second memory cells C0 and C1 may beprogrammed to one of the erase state, the PV1 state, the PV2 state, andthe PV3 state. For example, when the first memory cell C0 is selected tobe programmed into the PV1 state and the second memory cell C1 isselected to be programmed to the PV2 state, because the same programvoltage Vpgm is applied to the first memory cell C0 and the secondmemory cell C1 at the same time, the first program operation may beperformed such that the first and second memory cells are programmed tothe PV1 state. For instance, ISSP-type program voltages Vpgm may beapplied to the first word line W0 and the second word line W1 at thesame time, and it is determined whether the first memory cell C0selected to be programmed into the PV1 state has been programmed intothe PV1 state by a program verification operation. If the first memorycell C0 has not been programmed, the program voltage Vpgm is increasedby a step voltage and then applied to the first word line W0 and thesecond word line W1. If it is determined, as a result of the programverification, that the first memory cell C0 has been programmed into thePV1 state, the page buffer PB1 applies a program inhibit voltage to thefirst bit line BL1 of the first memory string ST1. The same programoperation performed on the first memory cell C0 may be performed on thesecond memory cell C1 so that the second memory cell C1 may beprogrammed to have a similar threshold voltage distribution to the firstmemory cell C0. The threshold voltage distribution of the second memorycell C1 may be lower than the PV2 state to which the memory cell isfinally programmed.

That is, when it is determined that one of at least two selected memorycells among the plurality of memory cells included in one memory stringhas been programmed, it is determined that the first program operationperformed on the at least two selected memory cells has been completed,and then a program inhibit voltage is applied to the bit line of thecorresponding memory string coupled to the at least two selected memorycells.

When, like the first program operation for the first memory string ST1that has passed a program verification check, it is determined that thefirst program operation for all of the second to m^(th) memory stringsST2 to STm has passed the program verification, and thus a programinhibit voltage is applied to all of the bit lines BL1 to BLm of theplurality of memory strings ST1 to Stm, and the first program operationis completed.

If the first program operation is completed, the second programoperation is performed. The second program operation may be performed onthe first and second pages PAGE_0 and PAGE_1, which were selected duringthe first program operation, page by page in a predetermined order. Forexample, a program operation for the first page PAGE_0 may be performedby applying a program voltage Vpgm that is increased stepwise (i.e., theISPP), and if it is determined that the program verification for thefirst page PAGE_0 has passed, a program operation for the second pagePAGE_1 is performed using the ISPP method.

Here, a start program voltage Pgm Start Bias of the first programoperation and a start program voltage Pgm Start Bias of the secondprogram operation may be set to be the same. Alternatively, the lastprogram voltage Vpgm applied during the first program operation may beset to the first program voltage Vpgm of the second program operation.

For example, in the first program operation, if the first memory cell C0has been programmed into the PV1 state (e.g., the first memory cell C0has passed a program verification), and the second memory cell C1 hasnot been programmed into the PV2 state, the last program voltage Vpgmapplied during the first program operation is applied to the secondmemory cell C1 as the first program voltage Vpgm of the second programoperation. As a result, the threshold voltage of the second memory cellC2 may increase from the PV1 state to be programmed into the PV2 stateduring the second program operation. Here, because a start programvoltage Vpgm of the second program operation may be set to be higherthan a start program voltage Vpgm of the first program operation, thenumber of iterations of program pulse applications needed to completethe program operations may be reduced, and thus the time it takes toperform the program operation may be reduced.

Alternatively, a voltage level increased by a step voltage from the lastprogram voltage Vpgm of the first program operation may be set as thestart program voltage Vpgm of the second program operation.

As described above, in the case where the first program operation for atleast two pages is performed at once and thereafter the second programoperation of programming the selected pages is performed one at a time,the time it takes to perform the second program operation may bereduced, and thus the total time it takes to perform the first andsecond program operations may be reduced.

FIG. 3 is a flowchart illustrating an example of the program operationof the semiconductor memory device according to an embodiment of thepresent disclosure.

Referring to FIGS. 1, 2 and 3, a program command and address informationmay be input from an external device (at S110). A plurality of data bitsDATA to be programmed may be input to page buffers PB1 to PBm of thepage buffer circuit 130 (at S120). Depending on the data bits input tothe page buffers PB1 to PBm, potential levels of the bit lines BL1 toBLm coupled to the memory cell array 110 may be controlled.

After the step S120, the first program operation may be performed. Inthe first program operation, a program voltage Vpgm may be applied atthe same time to at least two selected word lines among the word linesWL0 to WLn coupled to the plurality of memory cells of the memory cellarray 110 (at S130).

After the step S130, if it is determined that with regard to each of theplurality of memory strings ST1 to STm at least one of the selectedmemory cells coupled to the selected word lines has been programmed(i.e., at least one of the selected memory cells coupled to the selectedword lines has passed its program verification), it may be determinedthat all the memory cells of the memory string including the programmedmemory cell have passed their program verifications (at S140), and aprogram inhibit voltage may be applied to the bit line of the memorystring. If there is no memory string that has passed a programverification, another program voltage Vpgm increased by a step voltagemay be applied to the selected word lines (at S150).

If all the memory strings ST1 to STm have passed their programverifications, the first program operation is completed (at S160). Ifthere is any memory string that has not passed its program verification,the steps S130, S140 and S150 are repeatedly performed.

After the first program operation has been completed, the second programoperation may be performed. In the second program operation, a programvoltage Vpgm may be applied to each of the selected word lines one at atime in a predetermined order. That is, the second program operation ofsuccessively programming the plurality of pages corresponding to theselected word lines is performed. Here, a start program voltage PgmStart Bias that is a program voltage first applied to the selected wordlines during the first program operation may be applied as a startprogram voltage Pgm Start Bias of the second program operation (atS170).

The second program operation may be performed on a page basis. If allmemory cells coupled to a selected word line have been programmed, asubsequent page may be selected, and then a program operation may beperformed on the subsequent page. When the program operation for theselected pages is completed, the second program operation is completed(at S180).

During the second program operation, in the program operation for eachpage, if at least one among the memory cells included in a selected pageis not programmed, the program voltage Vpgm may be increased stepwise(i.e., ISPP) and the increasing program voltages Vpgm may be applied toa selected word line (at S190).

FIG. 4 is a diagram illustrating the voltage levels of program pulsesapplied to the selected word lines according to an embodiment of thepresent disclosure.

In an embodiment, the program operation may be performed on the MLC thatstores two bits of data in a unit cell.

Referring to FIG. 4, the program operation may be performed using theISPP, and thus the program voltage Vpgm may be increased stepwise fromthe start program voltage Pgm Start Bias by a step voltage. Averification voltage Vverify may be applied in a period of time betweenpoints in time when respective program voltages Vpgm are applied.

According to an embodiment, the start program voltage Pgm Start Bias ofthe first program operation period and the start program voltage PgmStart Bias of the second program operation period may be set such to bethe same as each other.

For example, during the first program operation, a program voltage Vpgmmay be applied at the same time to at least two selected word lines ofthe plurality of word lines of the memory cell array. The start programvoltage Pgm Start Bias of the first program operation may be set to 15Vthat is set at the initial stage. After the first program operation hasbeen completed, the second program operation may be performed. In thesecond program operation, a program voltage Vpgm may be applied to eachof the selected word lines, which were selected during the first programoperation, one at a time in a predetermined order. The start programvoltage Pgm Start Bias of the second program operation may be set to 15Vthat is the start program voltage Pgm Start Bias of the first programoperation.

FIG. 5 is a flowchart illustrating an example of a program operation ofa semiconductor memory device according to an embodiment of the presentdisclosure.

Referring to FIGS. 1, 2 and 5, a program command and address informationmay be input from an external device (at S210). A plurality of data bitsDATA to be programmed may be input to the page buffers PB1 to PBm of thepage buffer circuit 130 (at S220). Depending on the data bits DATA inputto the page buffers PB1 to PBm, potential levels of the bit lines BL1 toBLm coupled to the memory cell array 110 may be controlled.

After the step S220, the first program operation may be performed. Inthe first program operation, a program voltage Vpgm may be applied atthe same time to at least two selected word lines among the word linesWL0 to WLn coupled to the plurality of memory cells of the memory cellarray 110 (at step S230).

After the step S130, if it is determined that with regard to each of theplurality of memory strings ST1 to STm at least one of the selectedmemory cells coupled to the selected word lines has been programmed(i.e., at least one of the selected memory cells coupled to the selectedword lines has passed its program verification), it may be determinedthat all the memory cells of the memory string including the programmedmemory cell have passed their program verifications (at S240), and thena program inhibit voltage may be applied to the bit line of the memorystring. If it is determined that each memory string has not passed aprogram verification, another program voltage Vpgm increased by a stepvoltage may be applied to the selected word lines (at S250).

If it is determined that all the memory strings ST1 to STm have passedtheir program verifications, the first program operation is completed(at S260). If there is any memory string that has not passed its programverification, the steps S230, S240 and S250 are repeatedly performed.

After the first program operation has been completed, the second programoperation may be performed. In the second program operation, a programvoltage Vpgm may be applied to each of the selected word lines one at atime in a predetermined order. That is, the second program operation ofsuccessively programming the plurality of pages corresponding to theselected word lines is performed. Here, the last program voltage Vpgmapplied during the first program operation to the selected word linesmay be applied as a start program voltage Pgm Start Bias of the secondprogram operation (at S270).

Alternatively, a voltage level increased by a step voltage from the lastprogram voltage Vpgm of the first program operation may be set as thestart program voltage Pgm Start Bias of the second program operation.

The second program operation may be performed on a page basis. If allmemory cells coupled to a selected word line have been programmed, asubsequent page may be selected, and then a program operation may beperformed on the subsequent page. When the program operation for theselected pages is completed, the second program operation is completed(at S280).

During the second program operation, in the program operation for eachpage, if at least one memory cell among the memory cells included in apage selected is not programmed, the program voltage Vpgm may beincreased stepwise (i.e., ISPP) and the increasing program voltages Vpgmmay be applied to a selected word line (at S290).

FIG. 6 is a diagram illustrating the voltage levels of program pulsesapplied to the selected word lines according to an embodiment of thepresent disclosure.

In an embodiment, the program operation may be performed on the MLC thatstores two bits of data in a unit cell.

Referring to FIG. 6, the program operation may be performed using theISPP, and thus the program voltage Vpgm may be increased stepwise fromthe start program voltage Pgm Start Bias by a step voltage. Averification voltage Vverify may be applied in a period of time betweenpoints in time when respective program voltages Vpgm are applied.

According to an embodiment, the last program voltage of the firstprogram operation period may be set as the start program voltage PgmStart Bias of the second program operation.

For example, during the first program operation, a program voltage Vpgmmay be applied at the same time to at least two selected word lines ofthe plurality of word lines of the memory cell array, and the lastprogram voltage Vpgm applied when the first program operation iscompleted may be 16V. After the first program operation has beencompleted, the second program operation may be performed. In the secondprogram operation, a program voltage Vpgm may be applied to each of theselected word lines, which were selected during the first programoperation, one at a time in a predetermined order. The start programvoltage Pgm Start Bias of the second program operation may be set to 16Vthat is the last program voltage of the first program operation, whichis applied when the first program operation is completed.

While the spirit and scope of the present disclosure are described byembodiments, it should be noted that the above-described embodiments aremerely descriptive and should not be considered limiting. Further, itshould be understood by those skilled in the art that various changes,substitutions, and alternations may be made herein without departingfrom the scope of the disclosure as defined by the following claims.

FIG. 7 is a diagram illustrating an example of a memory system includingthe semiconductor memory device of FIG. 1.

Referring FIG. 7, the memory system 1000 may include a semiconductormemory device 100 and a controller 1100.

Configurations and operations of the semiconductor memory device 100 maybe the same as those of the semiconductor memory device described withreference to FIG. 1, and thus any repetitive detailed description willbe omitted or simplified.

The controller 1100 may be coupled to a host Host and the semiconductormemory device 100. In response to a request from the host Host, thecontroller 1100 may access the semiconductor memory device 100. Forexample, the controller 1100 controls read, write, erase, and backgroundoperations of the semiconductor memory device 100. The controller 1100may provide an interface between the host and the semiconductor memorydevice 100. The controller 1100 may drive firmware for controlling thesemiconductor memory device 100.

The controller 1100 may include a random access memory (RAM) 1110, aprocessing unit 1120, a host interface 1130, a memory interface 1140,and an error correction block 1150. The RAM 1110 may be used as at leastone of an operation memory of the processing unit 1120, a cache memorybetween the semiconductor memory device 100 and the host, and a buffermemory between the semiconductor memory device 100 and the host. Theprocessing unit 1120 may control the overall operation of the controller1100. In addition, the controller 1100 may temporarily store programdata provided from the host Host during the write operation.

The host interface 1130 may include a protocol for performing dataexchange between the host Host and the controller 1100. In anembodiment, the controller 1200 may communicate with the host through atleast one of various interface protocols such as a universal serial bus(USB) protocol, a multimedia card (MMC) protocol, a peripheral componentinterconnection (PCI) protocol, a PCI-express (PCI-E) protocol, anadvanced technology attachment (ATA) protocol, a serial-ATA protocol, aparallel-ATA protocol, a small computer small interface (SCSI) protocol,an enhanced small disk interface (ESDI) protocol, and an integrateddrive electronics (IDE) protocol, a private protocol, and the like.

The memory interface 1140 may interface with the semiconductor memorydevice 100. For example, the memory interface may include a NANDinterface or NOR interface.

The error correction block 1150 may use an error correction code (ECC)to detect and correct an error in data received from the semiconductormemory device 100. In an embodiment, the error correction block may beprovided as an element of the controller 1100.

The controller 1100 and the semiconductor memory device 100 may beintegrated into a single semiconductor device. In an embodiment, thecontroller 1100 and the semiconductor memory device 100 may beintegrated into a memory card. For example, the controller 1100 and thesemiconductor memory device 100 may be integrated into a memory cardsuch as a personal computer memory card international association (e.g.,PCMCIA), a compact flash card (CF), a smart media card (e.g., SM orSMC), a memory stick multimedia card (e.g., MMC, RS-MMC, or MMCmicro), aSD card (e.g., SD, miniSD, microSD, or SDHC), a universal flash storage(UFS), and the like.

The controller 1100 and the semiconductor memory device 100 may beintegrated into a single semiconductor device to form a solid statedrive (SSD). The SSD includes a storage device formed to store data in asemiconductor memory.

In an embodiment, the memory system 1000 may be provided as one ofvarious elements of an electronic device such as a computer, a ultramobile PC (UMPC), a workstation, a net-book, a personal digitalassistants (PDA), a portable computer, a web tablet, a wireless phone, amobile phone, a smart phone, an e-book, a portable multimedia player(PMP), a game console, a navigation device, a black box, a digitalcamera, a 3-dimensional television, a digital audio recorder, a digitalaudio player, a digital picture recorder, a digital picture player, adigital video recorder, a digital video player, a device capable oftransmitting/receiving information in an wireless environment, one ofvarious devices for forming a home network, one of various electronicdevices for forming a computer network, one of various electronicdevices for forming a telematics network, an RFID device, one of variouselements for forming a computing system, or the like.

In an embodiment, the semiconductor memory device 100 or the memorysystem 1000 may be embedded in various types of packages. For example,Examples of the packages may include Package on Package (PoP), Ball gridarrays (BGAs), Chip scale packages (CSPs), Plastic Leaded Chip Carrier(PLCC), Plastic Dual In Line Package (PDIP), Die in Waffle Pack, Die inWafer Form, Chip On Board (COB), Ceramic Dual In Line Package (CERDIP),Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), SmallOutline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline(TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi ChipPackage (MCP), Wafer-level Fabricated Package (WFP), Wafer-LevelProcessed Stack Package (WSP), or the like.

FIG. 8 is a diagram illustrating an application example of the memorysystem of FIG. 7.

Referring FIG. 8, the memory system 2000 may include a semiconductormemory device 2100 and a controller 2200. The semiconductor memorydevice 2100 may include a plurality of memory chips. The semiconductormemory chips may be divided into a plurality of groups.

In FIG. 8, it is illustrated that each of the plurality of groupscommunicates with the controller 2200 through first to k-th channels CH1to CHk. Each semiconductor memory chip may operate in the same manner asthat of an embodiment of the semiconductor memory device 100 describedwith reference to FIG. 1.

Each group may communicate with the controller 2200 through one commonchannel. The controller 2200 may have the same configuration as that ofthe controller 1100 described with reference to FIG. 8, and may controla plurality of memory chips of the semiconductor memory device 2100through the plurality of channels CH1 to CHk.

FIG. 9 is a diagram illustrating an example of a computing systemincluding the memory system illustrated with reference to FIG. 8.

Referring to FIG. 9, the computing system 3000 may include a centralprocessing unit 3100, a RAM 3200, a user interface 3300, a power supply3400, a system bus 3500, and a memory system 2000.

The memory system 2000 may be electrically coupled to the CPU 3100, theRAM 3200, the user interface 3300, and the power supply 3400 through thesystem bus 3500. Data provided through the user interface 3300 orprocessed by the CPU 3100 may be stored in the memory system 2000.

In FIG. 9, the semiconductor memory device 2100 is illustrated as beingcoupled to the system bus 3500 through the controller 2200. However, thesemiconductor memory device 2100 may be directly connected to the systembus 3500. The function of the controller 2200 may be performed by theCPU 3100 and the RAM 3200.

In FIG. 9, the memory system 2000 described with reference to FIG. 8 isillustrated as being provided. However, the memory system 2000 may bereplaced with the memory system 1000 described with reference to FIG. 7.In an embodiment, the computing system 3000 may include all the memorysystems 1000 and 2000 described with reference to FIGS. 7 and 8.

According to an embodiment of the present disclosure, a program voltageis applied to a plurality of word lines at the same time, and then aprogram voltage is successively applied to each of the selected wordlines. Therefore, the number of iterations of program pulse applicationsneeded to complete the program operations may be reduced, and thus thetime it takes to perform the program operation may decrease.

While embodiments of the present disclosure have been disclosed forillustrative purposes, those skilled in the art will appreciate thatvarious modifications, additions and substitutions are possible.Therefore, the scope of the present disclosure must be defined by theappended claims and equivalents of the claims rather than by thedescription preceding them.

What is claimed is:
 1. A semiconductor memory device comprising: amemory cell array including a plurality of memory strings; peripheralcircuits configured to program the memory cell array; and a controllogic configured to control the peripheral circuits, wherein the controllogic controls the peripheral circuits for performing a first programoperation by simultaneously applying a program voltage that sequentiallyincreases to at least two selected word lines, among a plurality of wordlines of the memory cell array.
 2. The semiconductor memory deviceaccording to claim 1, wherein the control logic controls the peripheralcircuits for performing a second program operation by applying theprogram voltage to one of the at least two selected word lines after thefirst program operation.
 3. The semiconductor memory device according toclaim 1, wherein the control logic controls the peripheral circuits forperforming a second program operation by applying the program voltage bysequentially selecting the at least two selected word lines after thefirst program operation.
 4. The semiconductor memory device according toclaim 1, wherein the control logic controls the peripheral circuits suchthat, for each of the plurality of memory strings, when at least one ofselected memory cells coupled to the at least two selected word lines isprogrammed, it is determined that a corresponding memory string haspassed a program verification.
 5. The semiconductor memory deviceaccording to claim 4, wherein the control logic controls the peripheralcircuits such that if it is determined that all the memory strings havepassed their program verifications, the first program operation iscompleted.
 6. The semiconductor memory device according to claim 4,wherein the control logic controls the peripheral circuits such that aprogram inhibit voltage is applied to a bit line of the memory stringthat has passed a program verification.
 7. The semiconductor memorydevice according to claim 3, wherein the first program operation and thesecond program operation are performed by using an incremental steppulse program (ISPP).
 8. The semiconductor memory device according toclaim 7, wherein the control logic controls the peripheral circuits bysetting a last program voltage of the first program operation as a startprogram voltage of the second program operation or setting a voltagelevel increased by a step voltage from the last program voltage of thefirst program operation as the start program voltage of the secondprogram operation.
 9. The semiconductor memory device according to claim7, wherein the control logic controls the peripheral circuits such thata start program voltage of the first program operation and a startprogram voltage of the second program operation are equal to each other.10. A semiconductor memory device comprising: a memory cell arrayincluding a plurality of memory blocks; peripheral circuits configuredto program the memory cell array; and a control logic configured tocontrol the peripheral circuits for performing a first program operationby simultaneously applying a program voltage to at least two word lines,among a plurality of word lines coupled to a selected memory block,among the plurality of memory blocks.
 11. The semiconductor memorydevice according to claim 10, wherein the selected memory block includesa plurality of memory strings, and the control logic controls theperipheral circuits such that, for each of the plurality of memorystrings, when at least one memory cell, among at least two memory cellscoupled to the at least two word lines, is programmed, a correspondingmemory string is determined as a program path.
 12. The semiconductormemory device according to claim 11, wherein the control logic controlsthe peripheral circuits for performing a second program operation byapplying the program voltage by sequentially selecting each of the atleast two word lines after the first program operation when theplurality of memory strings are determined as program paths.
 13. Thesemiconductor memory device according to claim 12, wherein the firstprogram operation and the second program operation are performed usingan incremental step pulse program (ISPP).
 14. The semiconductor memorydevice according to claim 13, wherein the control logic controls theperipheral circuits by setting a last program voltage of the firstprogram operation as a start program voltage of the second programoperation or setting a voltage level increased by a step voltage fromthe last program voltage of the first program operation as the startprogram voltage of the second program operation.
 15. The semiconductormemory device according to claim 13, wherein the control logic controlsthe peripheral circuits such that a start program voltage of the firstprogram operation and a start program voltage of the second programoperation are equal to each other.
 16. A semiconductor memory devicecomprising: a memory cell array including a plurality of memory strings;peripheral circuits configured to program the memory cell array; and acontrol logic configured to control the peripheral circuits, wherein thecontrol logic controls the peripheral circuits for performing a firstprogram operation by using an incremental step pulse program (ISPP)method with a program voltage that sequentially increases and forsimultaneously applying the program voltage to at least two selectedword lines, among a plurality of word lines of the memory cell array.17. The semiconductor memory device according to claim 16, wherein thecontrol logic controls the peripheral circuits for performing a secondprogram operation by applying the program voltage by sequentiallyselecting each of the at least two selected word lines after the firstprogram operation.
 18. The semiconductor memory device according toclaim 17, wherein the control logic controls the peripheral circuitssuch that, for each of the plurality of memory strings, when at leastone of selected memory cells coupled to the at least two selected wordlines is programmed, it is determined that a corresponding memory stringhas passed a program verification.
 19. The semiconductor memory deviceaccording to claim 17, wherein the control logic controls the peripheralcircuits by setting a last program voltage of the first programoperation as a start program voltage of the second program operation orsetting a voltage level increased by a step voltage from the lastprogram voltage of the first program operation as the start programvoltage of the second program operation.
 20. The semiconductor memorydevice according to claim 17, wherein the control logic controls theperipheral circuits such that a start program voltage of the firstprogram operation and a start program voltage of the second programoperation are equal to each other.